IO/ESD circuit designer

Job Description:
Solid understanding of related CMOS process such as 90nm, 55nm, 40nm
IO circuit design methodology, flow, concept, and good understanding of analog circuit, ESD, and LU
Preferred experience in design and development of GPIO’s, USB
Excellent communication skills in interactions with internal R&D teams
Familiar with MCU is a plus
Responsibilities:
Circuit design including GPIO and special IO’s, layout guide, SOC project support
Qualification:
Experience required: 3+ year
Education: Bachelor/Master/PhD

薪资按照个人实际工作能力和技术水平来评定。
职位福利：五险一金、年底双薪、年终分红、餐补、带薪年假、周末双休、定期体检、员工旅游