职位描述
Responsibility:
- Taking charge of development & deployment of verification methodology
- Developing the verification suite using proper verification methodologies and tools
- Planning & execution of system and block level verification
- Working with multi team (design, etc) to meet quality requirment at system and block level
- Working with design & architecture teams to understand functionality of logic blocks
Qualification:
- BSEE & 5+ years ASIC Verification experience (MSEE preferred)
- Strong verification with SystemVerilog based OVM / UVM, VMM or related methodology
- High-speed design / verification experience
- Strong background defining cover groups, assertions, coverage driven verification concepts, etc.
- High-level transaction level modeling language experience
- C / C++ & Verilog / VHDL / Logic Design experience
- Software/hardware co-simulation experience is a plus
- Emulation experience is a plus
- Verification of multi-power domain designs, ideally using CPF / UPF
- SOC Architecture design and implementation knowledge
- Scripting language experience (i.e. Perl, Shell, Python)
- HW behavioral modeling in SystemC, C/C++, etc is a plus.
- Good at trouble-shooting
- Good learning record
- Good communication skill
- Taking charge of development & deployment of verification methodology
- Developing the verification suite using proper verification methodologies and tools
- Planning & execution of system and block level verification
- Working with multi team (design, etc) to meet quality requirment at system and block level
- Working with design & architecture teams to understand functionality of logic blocks
Qualification:
- BSEE & 5+ years ASIC Verification experience (MSEE preferred)
- Strong verification with SystemVerilog based OVM / UVM, VMM or related methodology
- High-speed design / verification experience
- Strong background defining cover groups, assertions, coverage driven verification concepts, etc.
- High-level transaction level modeling language experience
- C / C++ & Verilog / VHDL / Logic Design experience
- Software/hardware co-simulation experience is a plus
- Emulation experience is a plus
- Verification of multi-power domain designs, ideally using CPF / UPF
- SOC Architecture design and implementation knowledge
- Scripting language experience (i.e. Perl, Shell, Python)
- HW behavioral modeling in SystemC, C/C++, etc is a plus.
- Good at trouble-shooting
- Good learning record
- Good communication skill
职位福利：五险一金、年底双薪、绩效奖金、股票期权、餐补、带薪年假、补充医疗保险、定期体检
