Digital Design Engineer

· Requirements:
1. 3-5 years in RTL Design for high-speed SerDes (such as PCIe/Ethernet/MIPI/USB) PHY.
2. Understanding of PHY digital components like Clock Dividers and Synchronizers.
3. Familiarity with Low Power Design (Clock Gating) in high-speed logic.
4. Skilled in Verilog and module-level Static Timing Analysis (STA).
5. Experience in implementing DFT for high-speed links.
· Job Description:
1. Implement and refine PHY logic modules according to project specifications.
2. Develop Speed/Power Change State Machines to support multi-rate operations.
3. Develop Digital Loopback and Diagnostic Features for the PHY subsystem.
4. Maintain Register Maps for PHY configuration and sideband management.
5. Assist in Gate-level Simulations to verify physical layer reset and timing.