Digital Verification Engineer/Expert (SerDes)

· · Requirements:
1. 5+ years of experience in SerDes (such as PCIe/Ethernet/MIPI/USB) PHY-level Digital Verification.
2. Expertise in SerDes PHY verification environment buildup.
3. Proficient in SystemVerilog/UVM and Assertion-Based Verification (SVA).
4. Experience in verifying Clock Switching and Reset Sequences.
5. Strong ability to analyze complex waveforms and identify protocol violations.
· Job Description:
1. Verify the interface between the PHY and the Controller.
2. Develop testsets for Link Training, Loopback, and Protocol Compliance …etc.,
3. Ensure the PHY handles abnormal link conditions and abnormal signal robustly.
4. Define and achieve Functional Coverage goals for the PHY digital layer.