Design Architect/Expert (Chiplet/HBM/DDR)

Job Description (Responsibilities):
1. Define top-level Subsystem specifications, including Forwarded Clock architecture, reset sequences, and Power Management strategies.
2. Standardize interface protocols by defining signal requirements and timing to ensure seamless integration between Controller and PHY modules.
3. Build system-level performance models to evaluate bandwidth and latency, analyzing the impact of CRC overhead, and Retry mechanisms.
4. Drive the technical roadmap for product development and architect proprietary micro-architecture to meet specific SoC requirements.
5. Act as the technical bridge between Digital, Analog, and Physical Implementation teams to resolve compensation issues arising from SI/PI.
Requirements:
1. 10–15 years of experience in High-Speed Interface development and architecture (e.g., PCIe, CXL, HBM, Chiplet, DDR or USB).
2. Deep expertise in PCIe/Chiplet/HBM/Chiplet/DDR related protocol specifications.
3. Proven track record of successful Tape-out as integrator or leader.
4. Strong technical decision-making skills to balance complex PPA (Power, Performance, Area) trade-offs.
5. Expert-level capability in writing technical specifications and defining architectural blueprints.