Digital Verification Engineer

· Requirements:
1. 3-5 years of Digital Verification experience in SerDes PHY (such as PCIe/Ethernet/MIPI/USB).
2. Familiarity with Scrambling, Encoding, and Decoding logic verification.
3. UVM knowledge to maintain PHY-level Agents and Scoreboards.
4. Proficient in waveform analysis to trace digital logic failures.
5. Skilled in GLS to identify timing-related functional bugs in the PHY.
· Job Description:
1. Execute regressions and debug failures for the SerDes PHY subsystem.
2. Write and maintain SVA (Assertions) and Coverage Collectors.
3. Verify Overflow/Underflow mechanism.
4. Analyze coverage reports to close gaps in the physical layer verification.
5. Assist designers in debugging for edge-case scenarios.