Senior Digital Design Engineer/Expert

Job Description:
1. Design Bridges between the Controller and SoC buses such as AXI or NoC.
2. Design and implement proprietary Link Layer logic, including Retry mechanisms, Flow Control, and packet encapsulation.
3. Manage complex CDC (Clock Domain Crossing) between high-frequency data paths and asynchronous configuration paths.
4. Lead the convergence of Synthesis and STA for the Controller sub-block.
5. Supervise DEs in RTL development and maintain high-quality design documentation for the product library.
Requirements:
1. 5–8 years of Digital IC design experience, specializing in SerDes/High-Speed Interface Protocol Engine or Link Layer design (e.g., PCIe, CXL, HBM, Chiplet, DDR or USB).
2. Expert proficiency in Verilog/SystemVerilog and High-Speed FSM design.
3. Deep understanding of High-Speed Interface or SerDes protocol stacks and data integrity.
4. Proficient in EDA toolchains, such as Spyglass, Design Compiler, and PrimeTime.
5. Ability to perform Post-Silicon debug and complex ECO implementations.